Temperature Characterization of a Fully-synthesizable Rail-to-Rail Dynamic Voltage Comparator operating down to 0.15-V

This paper deals with the performance/temperature tradeoff in an ultra-low voltage, ultra-low power rail-to-rail dynamic voltage comparator made solely by digital standard cells. The digital nature of the comparator makes its design technology portable also enabling its operation at very low supply voltages down to deep sub-threshold. In particular, as sub-threshold circuits have a significant temperature dependence, this paper focuses on the comparator performance under different supply voltages and temperatures.Measurements performed on a 180nm testchip show correct operation under rail-to-rail common-mode input at a supply voltage ranging from 0.6V down to 0.15V. Moreover, the measurements under temperature variations of offset, clock-to-output delay, and power in the range from -25 °C to 75 °C show the respective performance trade-offs

Analog processing by digital gates: fully synthesizable IC design for IoT interfaces

Analog integrated circuits do not take advantage of scaling and are easily the bottleneck in terms of cost and performance in Internet of Things (IoT) sensor nodes integrated in nanoscale technologies. While this challenge is most commonly addressed by devising more “digital friendly” analog cells based on traditional design concepts, the possibility to translate analog functions into digital, so that to implement them by true digital gates, is now emerging as a promising alternative. This last approach, which challenges the idea that “analog circuits will be always needed”, is presented in this tutorial starting from the theoretical background to its application in digital-based operational amplifiers, voltage references, oscillators and data converters integrated on silicon which have proposed in recent literature. The applicability of the concepts to the design of ICs which are natively portable across technology nodes and highly reconfigurable, thus enabling dynamic energy quality scaling, as well as a low design effort and a fast time-to-market will be described

Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation

In Paper 5.2, the National University of Singapore and Politecnico di Torino present a capacitance-to-digital converter (CDC) for direct harvester-powered low-cost systems, showing a 7-bit ENOB down to 0.3V at 1.37nW power without any external reference or voltage-regulation requirements

A Sub-Leakage pW-Power Hz-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply

A pW-power versatile relaxation oscillator operating from sub-threshold (0.3V) to nominal voltage (1.8V) is presented, having Hz-range frequency under sub-pF capacitor. The wide voltage and low sensitivity of frequency/absorbed current to the supply allow the suppression of the voltage regulator, and direct powering from harvesters (e.g., solar cell, thermal from machines) or 1.2-1.5V batteries. A 180nm testchip exhibits a frequency of 4 Hz , 10%/V supply sensitivity at 0.3-1.8V, 8-18pA current, 4%/°C thermal drift from -20°C to 40°C

Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS

A 10-bit-400kS/s and a 10-bit-2MS/s Relaxation Digital to Analog Converters (ReDAC) in 40nm are presented in this paper. The two ReDACs operate from a 600mV power supply, occupy a silicon area of less than 1,000um^2. The first/second DAC achieve a maximum INL of 0.33/0.72 LSB and a maximum DNL of 0.2/1.27 LSB and 9.9/9.4 ENOB based on post-layout simulations. The average energy per conversion is less than 1.1/0.73pJ, corresponding to a FOM of 1.1/1.08 fJ/(conv. step), which make them well suited to Internet of Things (IoT) applications. (PDF) Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS. Available from: https://www.researchgate.net/publication/336552301_Design_of_Relaxation_Digital-to-Analog_Converters_for_Internet_of_Things_Applications_in_40nm_CMOS [accessed Nov 16 2019]

Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3V

A novel rail-to-rail dynamic voltage comparator is presented in this paper. The proposed circuit is fully synthesizable, as it can be designed with automated digital design flows and standard cells, and can operate at very low voltages down to deep sub-threshold. Post-layout simulations show correct operation for rail-to-rail common-mode inputs at a supply voltage VDD down to 0.3 V. At such voltage, the input offset voltage standard deviation is less than 28 mV (8 mV) over the rail-to-rail common-mode input range (around VDD/2). The digital nature of the comparator and its ability to operate down to deep sub-threshold voltages allow its full integration with standard-cell digital circuits in terms of both design and voltage domain. The ease of design, the low area and the voltage scalability make the proposed comparator very well suited for sensor nodes, integrated circuits for the Internet of Things and related applications

Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling

In this paper, a fully synthesizable digital-to-analog converter (DAC) is proposed. Based on a digital standard cell approach, the proposed DAC allows very low design effort, enables digital-like shrinkage across CMOS generations, low area at down-scaled technologies, and operation down to near-threshold voltages. The proposed DAC can operate at supply voltages that are significantly lower and/or at clock frequencies that are significantly greater than the intended design point, at the expense of moderate resolution degradation. In a 12-bit 40-nm testchip, graceful degradation of 0.3bit/100mV is achieved when V_DD is over-scaled down to 0.8V, and 1.4bit/100mV when further scaled down to 0.6V. The proposed DAC enables dynamic power-resolution tradeoff with 3X (2X) power saving for 1-bit resolution degradation at iso-sample rate (iso-resolution). A 12-bit DAC testchip designed with a fully automated standard cell flow in 40nm consumes 55µW at 27kS/s (9.1µW at 13.5kS/s) at a compact area of 500µm^2 and low voltage of 0.55V

Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation

In this work, a capacitance-to-digital converter (CDC) suitable for direct energy harvesting is introduced. The nW peak power and the ability to operate at any supply voltage in the 0.3-1.8 V range allow complete suppression of any intermediate DC-DC conversion, and hence direct supply provision from the harvester, as demonstrated with a mm-scale solar cell. The proposed CDC architecture eliminates the need for any additional support circuitry, preserving true nW-power operation, and reducing design and integration effort. In detail, the architecture is based on a pair of double-swappable oscillators, and avoids the need for any voltage/current/frequency reference circuit in the oscillator mismatch compensation. The digital and differential nature of the architecture counteracts the effect of process/voltage/temperature variations. A load-agnostic one-time self-calibration scheme compensates mismatch, and can be run from boot to run stage of the chip lifecycle. The proposed self-calibration scheme suppresses any trimming or testing time for low-cost systems, and avoids any input capacitance disconnection requirement. A 180-nm testchip shows 7-bit ENOB down to 0.3 V and 1.37-nW total power, when powered by a 1-mm2 indoor solar cell down to 10 lux (i.e., late twilight

Fully-Digital Rail-to-Rail OTA with Sub-1,000 μm2 Area, 250-mV Minimum Supply and nW Power at 150-pF Load in 180nm

A fully-digital operational transconductance amplifier (DIGOTA) architecture for tightly energy-constrained low-cost systems is presented. A 180nm DIGOTA testchip exhibits an area below the 1,000-μm2 wall, and 2.4-nW power under 150pF load, and a minimum supply voltage Vmin of 0.25 V. In the 0.3-0.5 V supply range, DIGOTA improves the areanormalized small (large) signal energy FoM by at least 836X (267X) over prior sub-500mV OTAs, while reducing area by 27-85X. The low-Vmin and nW-power features are shown to enable direct harvesting at the mm scale